The present invention relates to decoding apparatuses for decoding digital data, and more particularly to a decoding apparatus and a decoding method for decoding data which is composed of encoded variable-length codes.
Heretofore, regarding digital data expressive of an image by way of example, encoding techniques which comply with redundancy, and efficient encoding apparatuses/encoding methods as well as decoding apparatuses/decoding methods which correspond to the encoding techniques have been devised in large numbers, and Huffman encoding is also deemed one of the encoding techniques for mitigating the redundancy of the digital data.
Besides, decoding apparatuses and decoding methods which correspond to the Huffman encoding technique have hitherto been devised in large numbers.
Here, heightening the speed of decode processing is always posed as a problem in the decoding apparatus and decoding method corresponding to the Huffman encoding technique, as in the decoding apparatus for any other encoding technique.
Accordingly, the present invention has for its object to provide a decoding apparatus and a decoding method for variable-length codes in which data composed of variable-length codes generated by the Huffman encoding or the like is subjected to decode processing at a higher speed.
The present invention consists in a decoding apparatus for variable-length codes wherein input data which consist of a plurality of variable-length codes of at most N bits are decoded successively in a plurality of cycles, comprising:
a first logic circuit which receives the input data, and which delivers necessary-length data having the minimum number of bits that is a multiple of k and that exceeds N;
decode means connected to said first logic circuit, for delivering a data length of remaining data obtained by removing the first variable-length code contained in the necessary-length data, from said necessary-length data, and for decoding said necessary-length data in accordance with the remaining data in the preceding cycle and then outputting the decoded data; and
first control means connected to said decode means, for controlling said first logic circuit so as to receive the input data having the number of bits that is the multiple of k depending upon the data length of said remaining data;
wherein symbol N denotes a natural number of at least 2, and symbol k denotes a natural number smaller than the number N.
Besides, the present invention consists in a decoding apparatus for variable-length codes, wherein said decode means is constructed including:
storage means for prestoring therein reference data corresponding to the plurality of variable-length codes contained in said input data;
movement means for moving the reference data in accordance with said data length of said remaining data;
comparison means for comparing the received necessary-length data and said reference data moved by said movement means;
code discrimination means for discriminating and outputting the variable-length code contained in said input data, in accordance with a result of the comparison made by said comparison means, and for feeding said first control means with said data length of said remaining data; and
second control means for feeding said movement means with said data length of said remaining data as determined in accordance with a result of the discrimination made by said code discrimination means.
Besides, the present invention consists in a decoding apparatus for variable-length codes, wherein said decode means is constructed including:
a second logic circuit which concatenates the received necessary-length data with said remaining data in said preceding cycle;
storage means for prestoring therein reference data corresponding to the plurality of variable-length codes contained in said input data;
comparison means for (comparing data delivered from said second logic circuit and the reference data;
code discrimination means for discriminating and outputting the variable-length code contained in said input data, in accordance with a result of the comparison made by said comparison means, and for feeding said first control means with said data length of said remaining data; and
second control means for feeding said second logic circuit with said remaining data determined in accordance with a result of the discrimination made by said code discrimination means.
Further, the present invention consists in a decoding method for variable-length codes wherein input data which consist of a plurality of variable-length codes of at most N bits are decoded successively in a plurality of cycles, comprising:
computing from the input data, necessary-length data having the minimum number of bits that is a multiple of k and that exceeds N;
subjecting the necessary-length data to decode processing in accordance with remaining data in the preceding cycle;
computing a data length of the remaining data obtained by removing the first variable-length code contained in said necessary-length data, from said necessary-length data; and
controlling said input data so as to have the number of bits that is the multiple of k, in accordance with the data length of said remaining data;
wherein symbol N denotes a natural number of at least 2, and symbol k denotes a natural number smaller than the number N.
Besides, the present invention consists in a decoding method for variable-length codes, wherein said decode processing includes:
prestoring reference data corresponding to the plurality of variable-length codes contained in said input data;
moving the reference data in accordance with said data length of said remaining data;
comparing the received necessary-length data and the moved reference data; and
discriminating and outputting the variable-length code contained in said input data, in accordance with a result of the comparison, and computing said data length of said remaining data.
Besides, the present invention consists in a decoding method for variable-length codes, wherein said decode processing includes:
prestoring reference data corresponding to the plurality of variable-length codes contained in said input data;
concatenating the received necessary-length data with said remaining data in said preceding cycle;
comparing the concatenated data and said reference data; and
discriminating and outputting the variable-length code contained in said input data, in accordance with a result of the comparison, and computing said remaining data.